Static random access memory (SRAM) is a type of semiconductor memory that stores data in the form of bits using bistable circuitry without the need for refreshing. FIG. 1 is a circuit diagram of a known type of SRAM. FIG. 1 shows an SRAM memory cell 100 (also known as a bitcell) with six metal oxide semiconductor (MOS) transistors in a configuration known as 6T (six transistors), although SRAM configurations with other numbers of transistors are available as well. NMOS transistor 110 and PMOS transistor 120 are coupled to form an inverter, and NMOS transistor 130 and PMOS transistor 140 are coupled to form another inverter. The two inverters are cross-coupled to provide bistable memory storage, with a bit and its complement stored at nodes Q and Q_INV, respectively. PMOS transistors 120, 140 are coupled to a power supply voltage VDD, and NMOS transistors 110, 130 are coupled to a ground node. NMOS transistors 150, 160 are known as access transistors because they provide access to bit lines BL, BL_INV. A gate of each of the access transistors 150, 160 is coupled to a word line WL that controls whether the access transistors 150, 160 are connected to the bit lines BL, BL_INV.
The bit cell has three different states or modes of operation. In a standby mode, word line WL is not asserted, and access transistors 150, 160 are therefore disconnected from bit lines BL, BL_INV. The cross-coupled inverters formed by transistors 110, 120 and transistors 130, 140, respectively reinforce each other to maintain a bit and its complement at nodes Q and Q_INV, respectively. In a read mode, bit lines BL and BL_INV are initially precharged to a logical high value (‘1’). Then, word line WL is asserted, thereby enabling access transistors 150, 160. The data values stored at nodes Q, Q_INV are transferred to bit lines BL, BL_INV. For example, if the content of bit cell 100 is ‘1’ (i.e., if Q is ‘1’ and Q_INV is ‘0’), BL remains high and BL_INV is discharged through transistors 150 and 110 to a logical low value (‘0’). If the content of bit cell 100 is ‘0’, BL remains at ‘0’ and BL_INV is pulled up to ‘1’. In a write mode, the data value to be written to bit cell 100 is applied to bit lines BL, BL_INV by setting BL to the desired value and BL_INV to its complement. Then, word line WL is asserted, causing the desired value to be latched into the cross-coupled inverters.
FIG. 2 is a circuit diagram of a known word line decoder 200 configured to connect to SRAM bitcells in order to store multiple data bits. A plurality of word lines WL[0], WL[1],. . . , WL[31] are provided at the outputs of respective driver circuits 210-0, 210-1, . . . , 210-31 (generally 210), which may be logical AND gates. Each driver circuit 210 has a plurality of input lines that are coupled, e.g., using interconnects, to decoder lines DEA[0], DEA[1], DEB[0], DEB[1], and DEC[0], DEC[7] to determine whether the corresponding word line is asserted (at a logical high value). In FIG. 2, an example configuration with 32 word lines is shown; therefore, log232 (or 5) bits of information are used to select the driver circuits 210. In this example, the 5 bits are provided by decode lines DEA[0], DEA[1] contributing one bit of information, decode lines DEB[0], DEB[1] contributing one bit of information, and decode lines DEC[0], DEC[7] contributing three bits of information. Using three input lines in the example of FIG. 2, driver circuits 210 are thus presented with 32 different possible input combinations. For example, decode lines DEC[1], DEB[1], and DEA[1] are asserted (logical high) in order to assert word line WL[7].